Power Architecture Developer Conference Sessions

Please check back often, as we are continually adding sessions to the program. A daily schedule of sessions will be available shortly.

While the submission deadline has passed, the technical review committee will consider late submissions on a case by case basis, if you are interested in submitting a topic for consideration please contact PADCinfo@power.org

Conference Sessions by Discipline

Keynotes

The Value of the Power Architecture: The Power is in the Software!
Brian Wilkie, Vice President and Assistant General Manager of the Integrated Communications Products, AMCC.
Brian will talk about where the true value of Power Architecture technology lies: in the software. Despite, or perhaps because of, his many years in the semiconductor business, Brian will highlight the customer's view of the comparative investment in hardware and hardware tools, as against that in software, and software tools.
Enter the Era of Embedded Multi-core: No Longer at Your Own Risk
Lynelle McKay, Senior Vice President and General Manager, Networking & Computing Systems Group, Freescale Semiconductor.
Consumers are advancing the evolution of today's networks. Increasing user demands for secure access to online information, entertainment and collaboration – from any device, anywhere – have created the need for extensible equipment that enables rapid introduction of services over a converged network. Lynelle will address the vital role that multi-core platforms based on Power Architecture technology will play in assuring the flexibility and scalability of next-generation networks and debunk the myth that all cores are created equal.
Collaborative Innovation – Designing in the Broadband Era
Jim Kahle, IBM Fellow, Chief Architect and Director of Technology, Austin Based Design Center for the Cell Technology, IBM.
This presentation will focus on the Cell Broadband Engine™“ supercomputer on a chip.”A 64-bit, Power Architecture compatible, heterogeneous multi-core design that sets a new performance standard for games and multimedia applications, it exploits parallelism while achieving high frequency. The convergence of multiple factors, including workload specialization, digital media revolution, process technology and partnership with Sony and Toshiba, and Cadence, led to many collaborative innovations. Jim will provide an overview of the Cell architecture and the challenges faced, as well as how these challenges were addressed and successfully implemented in the Cell processor.
Postcards from Mars
Jim Bell, Associate Professor, Director of Graduate Studies Cornell University, Astronomy Department.
Prof. Jim Bell is the lead scientist for the Mars Exploration Rover Spirit and Opportunity Panoramic Camera imaging systems. In this presentation he will showcase some of the amazing images and other scientific results from the more-than-three-year adventures of the rovers on Mars and will discuss the future of both human and robotic space exploration.

Embedded Perspective

Industrial Network Protocols on Communications Processors
Donna Imam, Industrial Market Development Manager, Power Architecture Technology, Freescale Semiconductor.
This session highlights performance, flexibility and suitability of industrial network protocol implementation with Freescale's PowerQUICC family of communications processors on a production-ready, industry-standard COM Express development system.
PowerPC Embedded MMU and Cache Management
Ben Gibbs, Senior Consulting Engineer, Technonics, Inc.
The purpose of this session is to provide an overview and understanding of how the Memory Management Unit (MMU) and caches are defined by the PowerPC Book E Architecture. Topics such as selecting proper page size, translation look-aside buffer (TLB) configuration, address translation, cache configuration, cache coherency, and cache management instructions will be covered.
On-Chip Bus Architectures for Power Architecture
Marc Greenberg, Technical Marketing Manager, Denali Software, Inc.
In this session the attendees will learn about the on-chip bus architecture recommendations that were made in the Power.org Bus Architectures SubCommittee, the data that was used to make those decisions, and the future directions of on-chip bus interconnects.
System Design with the P.A. Semi PA6T-1682M
Mark Hayter, Chief System Architect and Sr. Director, System Engineering, P.A. Semi.
Presentation on the PA6T-1682M low-power features, I/O subsystem (protocol engine support, throughput, and latencies, offload engines), and memory subsystem performance. In addition there will be discussion on how the 1682M can support logical partitions & hardware separation, and present example system block diagrams.
Chaining on-chip Accelerators in Power Architecture
Parav Pandit, Module Lead, R&D Services, Communication Group, Mindtree Consulting Ltd. Bangalore, India
Security gateways using PowerQUICC microprocessors control the QUICC engine and security functions using device drivers and the OS networking stack. Such control mechanisms add to data paths and increase packet processing time. This presentation discusses one solution for minimizing overhead by enhancing the Power Architecture.
Integrating Power Architecture Core IP in Embedded SoCs
Pierre-Xavier Thomas, Director, Silicon Valley Design Center, IPextreme
This session will discuss how to efficiently integrate e200 cores into embedded applications. A description of the logical interfaces will highlight the various types of bus cycles that are seen on the system bus. Memory subsystems and e200 core registers will also be described.
Digital Processing with Power Architecture in Automotive
Rebeca Delgado, Field Applications Engineer, Freescale Semiconductor
This session provides insight into how the Power ISA Signal Processing Engine (SPE) function brings performance advantages for next-generation automotive powertrain control applications.
Titan - An Ultra High-perf., Power and Area-efficient Core
Steve Horne, Founder and Director of Research and Technology, Intrinsity, Inc.
Introducing the Titan core, an ultra-high perf. power-efficient 32-bit embedded core. Built in partnership with AMCC using Fast14 NDL domino logic technology, Titan achieves 3-4x the perf. of a synth. equivalent in the same process, and is designed for multicore implementations.
Integrated Multi-Application Safety Critical and Secure Systems
Tim Skutt, Software Architect, GE Aviation
Increases in processor capabilities enable computing modules that satisfy the needs of multiple safety critical and/or secure functions simultaneously. This presentation discusses unique issues for safety critical and secure functions, their magnitude, and ways to overcome the barriers.
WiMAX Based Solution for Infrastructure and CPE
Fawzi Behmann, Director of Strategic Marketing, NCSG, Freescale Semiconductor.
This session will provide a review of WiMAX/LTE technological advances towards 4G, roadmap of standard development/certification, design considerations for OFDM/OFDMA and Power Architecture solution positioning. The session concludes with Freescale's Power Architecture solutions for WiMAX infrastructure and Customer Premises Equipment (CPE).
Virtual Integration of PowerQUICC Firmware and Peripherals
Jim Kenney, Product Manager, Mentor Graphics
The Freescale PowerQUICC family of devices contains a host of flexible and powerful peripherals. In this session we will present tools and models for simulating and debugging firmware executing on the PowerPC core as it initializes and operates the PowerQUICC peripheral set.
Multi-protocol Mapping with PPC405EX processor
Victor Menasce,Chief Technical Officer, AMCC
Combo networking products are becoming common. These products typically carry heterogeneous interfaces. The protocol termination and mapping used to be done in hardware. The latest generation PPC405EX processor, offers a combination of higher frequency and low power.
New Verification Methods for Power Based SOC Designs
Joseph Rothman, Sr. Vice President, EVE-USA
This paper will explore SOC verification means, such as simulation, and compare/contrast other "newer" approaches, including impact of ISS and "hardware assisted verification". It will discuss the strengths/weakness of advances in acceleration, emulation.
New Developments in Real-Time Embedded Linux
Joerg Bertholdt, Director of Embedded Platforms, MontaVista Software
Developers and device designers who have been forced to use RTOSs to achieve the performance and functionality their products need will see how advances in commercial-grade Linux now deliver the performance required by real-time applications. This seminar will present details on new technology approaches used in real-time Linux implementations, performance levels attained by embedded Linux, and APIs for integrating real-time Linux with embedded applications. It will also examine open source projects and technologies on the horizon to see where real-time Linux is headed and how future offerings may benefit developers.
Integrating Power Architecture Core IP in SoCs
Pierre-Xavier Thomas, Director, Silicon Valley Design Center, IPextreme
This session will discuss how to efficiently integrate e200 cores into embedded applications. A description of the logical interfaces will highlight the various types of bus cycles that are seen on the system bus. Memory subsystems and e200 core registers will also be described.
Rapid Assembly of Power-Based SoCs
John Swanson, Product Manager, Synopsys
Synopsys will demonstrate the creation of a Power Architecture SoC subsystem incorporating PLB4 and AMBA IP. CoreAssembler will rapidly assemble a complete subsystem while eliminating assembly and configuration errors, reducing verification time and achieving high silicon quality-of-results.
Hands-On Workshop: Efficient Programming with the QUICC Engine Utility Tool for Freescale PowerQUICC™ Processors
Marvin Hill, Applications Engineer, Freescale Semiconductor.
Utilize the QUICC engine utility tool to set up configurations to generate driver code on the MPC8323E, MPC8321E, MPC8360E and MPC8358E communication processor. Show how to configure GbE, Utopia, TDM, etc processor interfaces.
High Performance Secure Embedded Computing for the Cell Broadband Processor
Maximino Aguilar, Sales Solutions Engineer, IBM.
The Cell Broadband Processor excels at high performance computing applications especially in the arena of signal and image processing. The trend in the Aerospace & Defense market segment is to migrate to common off the shelf (COTS) solutions. Along with higher dense computing requirements in support of full situation awareness drives the desire for an embedded Cell B.E. operating system. The Cell B.E. has many features such as cache locking and bandwidth reservation that are amenable to real time operating system concepts. Cell B.E. security features additionally allow for protecting sensitive information within the system. The asymmetric heterogeneous nature of the cores in the Cell/B.E. must also be taken into consideration for real time operating systems. By examining a multitude of areas and taking into consideration client needs a high performance secure embedded computing platform can be architected for the Cell B.E.

Digital Media

Digital Video Processing with Power Architecture Technology
Sergei Larin, & Alexandra Dopplinger, Freescale Semiconductor
This session analyzes digital video processing capabilities on Power Architecture platforms, including discussion of Power ISA features, such as Vector category that enable dramatic processing improvements. Freescale will also detail a new Power Architecture platform for vision applications.

Compute Intensive Solutions

Optimizing Radix-2 FFT Algorithm for PowerPC Architecture
Joe Eicher, Dir. Global Field Application Engineering, Thales Computers
A radix-2 Fast Fourier Transform algorithm is optimized for maximum performance on the PowerPC architecture with Altivec technology. The FFT algorithm methodology takes full advantage of PowerPC parallelism, accelerating performance up to eight times over standard architectures.
A Soft Computing Multi-core Solution for Image Restoration.
S.R.Chickerur, Sona College of Technology.
Digital Image restoration studies methods used to recover original scene from the degraded observations.We propose the solution to restore the image using neural network learning approach on a multi core architecture.(Cell BE architecture).and also for video restoration time permitting.
Implementing the Linux ADMA Interface for Embedded RAID with PowerPC
Haluk Aytac, Senior Solutions Architect, AMCC.
This session describes how the performance of a RAID system is accelerated using the new Linux Asynchronous DMA interface. The ADMA interface enables RAID data path tasks to be offloaded to DMA engines, resulting in a significant increase in data throughput. The high-performance PowerPC Linux RAID driver is discussed in detail.
Lattice QCD on the Cell Broadband Engine
Dirk Pleiter, DESY Zeuthen
We investigate the potential of the Cell BE for lattice QCD applications and report on the performance of relevant kernels on Cell hardware. We also present our concept for a massively parallel machine in which the Cell BEs are interconnected by a 3-dimensional torus network.
LittleFe: Portable Parallel Computing Platforms for Pedagogy
David Joiner, Kean University
We present a solution for teaching high performance computing that uses commodity technology to create light-weight, low-power consumption, low-cost portable clusters for classrooms and demonstrations. Little-Fe puts a functional cluster in the students hands for the cost of a well-equipped laptop.
P6 and Decimal Floating Point
Janis Johnson, Software Engineer, IBM - Steven Carlough, Development Engineer, IBM.
Many commercial applications require calculations in base ten. This talk covers decimal floating-point arithmetic and encodings in the IEEE 754R floating-point standard; POWER6 hardware support for IEEE 754R; and compiler and related support enabling standard use of decimal float in applications.
Clustering PS3s
Tim Wilcox, HPC, Terra Soft Solutions
Terra Soft Solutions has constructed a growing Cell cluster from PLAYSTATION3 appliances. This lightweight, low-cost cluster solution offers both limitations and incredible performance opportunities. The key to success is the balance of the two, using Yellow Dog Linux and Y-HPC.

Multi-core Solutions

Key Design Challenges and Opportunities for Controlling Power in a Multi-Core Design
Dac Pham, Director, Power Architecture Cores & Platforms, Freescale Semiconductor
This presentation addresses the key design challenges faced by today's SoC designers and the opportunities that system integration and multi-core provides. Challenges for multi-core systems will be discussed, as well as Freescale's approach to addressing issues with multi-core platforms.
Next Generation Multi-GHz Multi-Core Power Architecture CPU
Joe Chang, Director of CPU Development, AMCC
The Titan processor core builds on the software architecture of the PowerPC 440. Titan uses leading circuit design techniques and a new pipeline to achieve >2 GHz performance with only 2.5 watts of power. This talk details the architecture of the Titan processor, caches, and memory subsystem.
Performance Evaluation of SMP Power Architectures
Markus Levy, President, EEMBC
This presentation describes multi-core architectures and the different forms of concurrency that can be applied. It explains the structure of the patent-pending EEMBC benchmarks used to evaluate these forms of concurrency applied to Power Architecture devices.
Design of 2GHZ High Performace Low Power Dual-core Processor
Wei-han Lien, Senior Priciple Architect, PA Semi
In this session processor micro-architecture (pipeline stages, cache implementation, scheduling algorithm, & coherency protocols) will be presented as well as examples of low power micro-architecture/logical/circuit techniques. As well, there will be presentation of error handling mechanisms to achieve server grade reliability.
Hybrid Multi-core Debugging Solution on a Power Architecture Embedded Platform
Radu Farcas, Software Engineer, Freescale Semiconductor
This paper focuses on debugging techniques and development tools targeting a hybrid multi-core architecture. The solution covers kernel and application level debugging for the RTOSes that run in parallel on each core. The debugging solution presented applies to hybrid multi-core platforms embedding a Power ArchitectureTM core and an accelerator. The debugging solution will be presented on Freescale MPC5121e platform: an hybrid multi-core system-on-chip embedding two programmable cores: a PA e300 core and an audio accelerator.
TCP/IP Acceleration in Cell Broadband Engine Based Platforms
Mr. Badrinath Dorairajan, Aricent.
The advent of 10G Ethernet has greatly increased the server community's interest in network acceleration. Although the Cell BE processor was originally targeted for gaming consoles, it is also finding acceptance as a server platform. In this session, we explore acceleration models for adapting Cell BE-based servers to networking workloads.
ADL/uADL: A Comprehensive Microprocessor Modeling Framework
Hangsheng Wang & Brian Kahne, Freescale Semiconductor.
This paper presents ADL and uADL: two languages for architecture and microarchitecture specification and modeling. Compared to existing languages, the ADL/uADL modeling framework features improved model reuse, support for incremental/approximate modeling and reduced overall modeling complexity.
Multi-Core Software Design Challenges and Opportunities
Nasr Ullah, Mgr, Multicore System Performance, Modelling & Analysis, Freescale Semiconductor.
Multi-core platforms inherently create software design challenges. This session explores those challenges and discusses how cycle-accurate and functional simulation models can aid in software design. A demonstration of a model for a Freescale Power Architecture multi-core processor is included.
IBM POWER6 & Microprocessor Core Overview
Jeff Stuecheli & Bruce Ronchetti, IBM.
IBM POWER servers have long lead the industry in performance and innovative system features. The POWER6 design continues this tradition with a combination of leadership performance across a wide range of workloads, mainframe like reliability features, advanced power management, and hardware acceleration capabilities. The presentation will provide insight into these features, highlighting the impressive capabilities of the POWER architecture.
This presentation will also describe the implementation of the IBM POWER6™ microprocessor Core, the two-way simultaneous multithreaded (SMT) Core of the IBM POWER6™ dual-core chip.
Sourcery VSIPL++ for Cell B.E.
Jules Bergmann, Sourcery, CodeSourcery, Inc.
The Cell B.E. architecture provides excellent performance potential for signal and image-processing applications. Sourcery VSIPL++ is a high-level API that helps realizing this potential by careful management of the architecture's communication and parallel resources.
IBM POWER6 Management & Reliability
Michael Mack & Juan Rubio, IBM.
This presentation describes advanced power management features introduced in the IBM POWER6™ microprocessor. They provide detailed information to monitor and manage power, temperature, reliability and performance. The interface gives system software real-time access to sensors and controls, enabling flexible system management solutions.
Using Simulated Hardware to Debug Multi-core Software
Ross Dickson, Principal Technology Specialist, Virtutech.
This presentation outlines the challenges of developing software for multicore systems and the typical problems encountered when moving existing (embedded) software to a multicore and multiprocessor systems. We will describe a range of techniques for analyzing and debugging software on multiprocessor hardware. We will have an in-depth discussion about how simulated hardware can make the software debug task easier and facilitate the move from single processors to multicore.
Hybrid Multi-Processing with Embedded PowerPC 405 Cores in FPGAs
Dan Isaacs, Director Embedded PowerPC Processing Advanced Products Group, Xilinx.
In this session, the authors will present the current environment for embedded PowerPC FPGA-based multiprocessing, including an integrated approach to embedded systems design that includes both industry standard embedded processors, and PowerPC FPGA based processor architectures. A comparison of programming models for such applications will be presented, including the use of tightly coupled algorithmic accelerators functioning as co-processing engines. System architectural trade-offs will be discussed in terms of design flexibility, throughput and overall performance. The concept of hybrid multi-processing using hardware accelerated dual processors is highlighted by a streaming video application.
Parallelism, Power efficiency, and Programmability: Challenges for Future Architectures
Doug Burger, Associate Professor of Computer Sciences, University of Texas at Austin.
Multi-core processors have arisen due to power and superscalar scalability limitations, but may cause a programmability crisis, exacerbated by process variation, hard/soft errors, and design/verification complexity. This talk will describe architectural principles for addressing these issues.
Workbench On-Chip Debugging Freescale MPC8641D and other Multi-core Devices
Stephen Gooch, Alliances Technical Manager, Wind River.
In this session, you'll learn how to take advantage of the latest multicore and multiprocessor debugging technology from Wind River. We'll discuss how to overcome the challenges in debugging multiple cores and multiple processors. You'll discover the different technology approaches and the advantages and disadvantages of each solution. You'll find out how Wind River's patent-pending Workbench On-Chip Debugging solution will help you get your Freescale multicore and multiprocessing solutions to market faster. We will be demonstrating on the MPC8641D, tips and tricks to debugging running multiple environments.
Multi-core Design: Challenges and Opportunities
Dac Pham, Director, Power Architecture Cores & Platforms, Freescale Semiconductor.
This presentation addresses the key design challenges faced by today's SoC designers and the opportunities that system integration and multi-core provides. Challenges for multi-core systems will be discussed, as well as Freescale's approach to addressing issues with multi-core platforms.
Automotive Qualified Multi-core Microprocessor for Telematics and Industrial Control Systems
Jeff Maguire, Chief Architect, TSPG Infotainment Mulitmedia Telematics Operation, Freescale Semiconductor.
This presentation provides an in-depth look at the advantages of a multi-core microprocessor and its multiple uses in the telematics and industrial control markets. The technical aspects as well as the ecosystem that supports this innovative product are all covered by the chief architect, Jeff Maguire.
Multi-core Enablement - Panel
Moderator: Eric Heikkila, Director, Embedded Hardware & Systems, VDC
Tomas Evensen, CTO, Wind River Systems
Jim Ready, Founder & CTO and Founder, Monta Vista
David Kleidermacher, CTO, Green Hills
Michel Genard, VP Business Development, Virtutech

The subject of multi-core is gaining momentum and customers’ demands are increasing. This in turn places a major emphasis on software development environment. A distinguished panel of experts will discuss and debate important topics such as virtualization, debugging , partitioning and software simulation.
Freescale Simulation Technology
Knute Lingaard, Project Lead, Multicore Simulators, Senior Member Technical Staff, Freescale Semiconductor.
Multi-core platforms inherently create software design challenges whether it is related to coding new applications or porting from single-core solutions. This session explores the simulation technologies behind the cycle-accurate and functional simulation models that provide a basis for designing more effective software.
The Cmpware CMP-DK for the Cell BE
Steven A. Guccione, Chief Scientist, Cmpware, Inc.
A hands-on tutorial using the Cell BE version of the Eclipse-based Cmpware CMP-DK multicore toolkit. Application development topics include shared memory programming, mailbox message passing, system level optimization and SPU optimization.

Software Development

Using the GNU Toolchain to Build Power Architecture Applications
Mark Mitchell, Chief Sourcerer, CodeSourcery, Inc.
The GNU toolchain (GCC, G++, etc.) is often used to develop Power Architecture applications. This presentation will describe the latest improvements, exlain how to optimize code for the Power Architecture, and how to use unique features of the GNU Toolchain to target embedded systems.
Introduction to OpenEmbedded
Stelios Koroneos, Digital OPSiS.
OpenEmbedded is a tool which allows developers to create a fully usable Linux base for various embedded systems. This presenation will demonstrate how to get started with OE and build a linux distribution for Power Architecture based devices.
Unleashing the Power with Advanced Compiler Optimizations
Greg Davis, Technical Lead, Compilers, Green Hills Software.
This talk surveys some of the optimization techniques employed by the Green Hills compiler suite to generate the industry's smallest and fastest code for the Power Architecture processors. The presentation focuses on the optimizations that most effective as well as those that are novel, and how certain optimizations are targeted towards specific members of the Power Architecture family.
Migrating Little-Endian to Big-Endian Architectures
Doug McQuaid, Applications Engineer, Networking Systems Division, Freescale Semiconductor.
Migrating to a new platform may seem impossible when so much legacy software exists. But migration may be easier than you think. This presentation explores the issue of endianness, and suggests steps to ease migration from little-endian to big-endian architectures (for example: x86 to Power ISA). Specific architectural features supporting endianess conversions are discussed using real life Freescale Power Architecture cores as example. Certain real life scenarios related to little-endian peripheral devices in embedded designs like legacy ASICs, or PCI based chips are used to illustrate complexities that might be encountered. Target audience are software and firmware engineers, as well as project managers involved in endianess conversions.
Accelerated Verification of PowerPC Embedded SoCs
Brad Bryant, ASIC Project Manager, L3 Communications.
This presentation reviews the various verification challenges presented by embedded PPC SoC designs and how acceleration can be utilized to develop solutions.
Slimline Open Firmware
Heiko Schick & Hartmut Penner, IBM
This lab session will provide an overview of the design and structure of Slimline Open firmware which is an open source implementation of the IEEE Std 1275-1994. This session covers the functionality and uniques of SLOF as well as give the comparison of open source firmware implementations. Furthermore, the presentation will examine the platforms on which SLOF is used as firmware and show steps on how it could be ported to new platforms including device drivers.
LAB: Hands-On Workshop: How Fast Can You Run Linux 2.6 on Freescale PowerQUICC™ board? Architecture
Jay Azurin, Applications Engineer, Freescale Semiconductor.
During this hands-on lab you will run U-boot exercises with Linux 2.6 (Compile, Program NAND FLASH), walk through several Linux exercises (how to boot, compile kernel and more), walk through an IP forwarding and USB host demo, while utilizing the CodeWarrior development tool.

Virtualization

Virtualization on Power
Hollis Blanchard, PowerPC Kernel and Hypervisor Hacker, IBM.
A quick overview of virtualization and its benefits, and details on Power's CPU virtualization hardware support and issues found exploiting it, especially in open source software.
High Assurance Security for Power-based Embedded Systems
David Kleidermacher, Chief Technology Officer, Green Hills Software, Inc.
Exploration of how an RTOS was implemented to meet EAL -7 of the Common Criteria. Lessons learned, including how to validate security of Power hardware, will be shared. As well, a demonstration of how virtualization enables critical applications to coexist with Linux.
Virtualization Features of PWRficient 1682M
Olof Johansson, Principal Engineer, PA Semi.
The Power Architecture includes CPU features required to do powerful hypervisor implementations ranging from high-end enterprise systems to embedded devices. Besides the processor core, other system components must also be extended to provide the foundation for a stable and secure hypervisor environment. This presentation will cover the Power Architecture hypervisor features that are implemented on PA6T as well as what additional features exist in the I/O subsystem of PWRficient 1682M to complete the requirements for secure whole-system virtualization. Some examples on how existing hypervisors exploit these features, as well as interesting areas to explore in the future.
Xen Hypervisor for Cell Broadband Engine
Seung Mo Cho, Senior Engineer, Samsung Electronics.
We describe efforts of Xen implementation for Cell processor which consists of a simultaneous multi-threaded (SMT) PPE core and 8 SPE cores. Xen extensions for SMT and SPE management will be discussed. We also present the performance evaluation result against software video decoder.
IBM Power6 Partition Mobility
Dick Arndt, RS/6000 Platform Architect, IBM., Wolfram Sauer, Manager of Systems Architecture, IBM.
This paper presents Power Architecture extension for enhanced virtualization first implemented by the Power6 processor. Virtual Partition Memory enables the memory of a virtual server running in a logical partition to be completely virtualized by the Power Hypervisor. Enhancements to the timebase facility allow updates to the virtual timebase of a logical partition while maintaining consistency with other partitions in the system. After explaining these fundamental enhancements their role in implementing the new partition mobility function is described. Partition mobility allows the seamless migration of virtual servers from one physical Power6 system to another.

Birds of a Feather Sessions

BOFS: Software Development for Power Architecture
Panel.
BOFS: SOC Design Tools (EDA Tool Companies).
Panel.
BOFS: Power efficient Design (Power and Thermal Considerations)
Panel.
BOFS: Performance Optimization
Panel.

Silver Sponsors:	Mentor Graphics, MontaVista, Wind River
Bronze Sponsors:	Denali, e2v, EVE-USA, IPextreme, Lauterbach, LynuxWorks, P.A. Semi, Terra Soft Solutions, Tundra Semiconductor, VaST Systems Technology, Virtutech, Xilinx
Media Sponsors: