Power Architecture e200 z6 Core

Freescale Semiconductor, a founding member of Power.org and a driving force in the evolution of the Power Architecture since the original PowerPC, is the worlds leading supplier of 32-bit controllers. Freescales e200 family of Power Architecture cores are well proven in a range of embedded applications, including their popular MPC5500 series of automotive MCUs. Those same e200 cores are now available from IPextreme, enabling any SoC or ASSP designer to benefit from the Power Architecture.

Freescales e200 family of synthesizable, high-efficiency cores is intended for cost-sensitive, embedded real-time applications with significant performance requirements. The four e200 cores available through IPextremee200z0, e200z1, e200z3, and e200z6provide a range of features ideal for automotive, avionics, robotics, industrial control, medical devices, and compact networking applications.

Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.

The z6 core is the high-end member of the e200 core family and offers the following features:

* 7-stage pipeline with in-order execution
* Single-issue (one instruction issued per clock cycle)
* 32-bit Power Architecture Book E CPU core
* VLE for code density
* Unified 32-KB, 8-way set-associative cache
* 32-entry unified MMU
* SIMD and FPU for enhanced DSP support
* AMBA AHB 2.0 v6 bus interface
* Single-cycle execution for most instructions
* Integer and floating point multiply and multiply-accumulate in 3 clocks, fully pipelined
* Integer divide in 6 to 16 clocks, unpipelined
* 3-cycle loads
* 1 to 3-cycle branches
* Small branch target address cache (BTAC) to accelerate loops
* Nexus Class 3 support